The invention provides a versatile means of generating and handling interrupts to a processor. Typically, in the prior art, interrupt processing has used special hardware to receive and decode interrupts. For instance, an Input/Output (I/O) device might generate an interrupt by assertion of an interrupt vector on a special bus. The interrupt vector might consist of two portions, an interrupt priority and a vector table index. If the interrupt priority exceeds a current priority of the processor, a program counter is loaded with an instruction address obtained from an indexed entry in a vector table.
The above-discussed method of interrupt processing has certain disadvantages. For instance, special bus protocols and hardware are required to implement interrupts. Also, when hardware is vectoring one interrupt, additional lower priority interrupts are not processed. Furthermore, interrupt priorities cannot be easily reassigned. Additionally, a special instruction is required for a processor to generate interrupts.